`ifndef VERILATOR
module testbench;
  reg [4095:0] vcdfile;
  reg clock;
`else
module testbench(input clock, output reg genclock);
  initial genclock = 1;
`endif
  reg genclock = 1;
  reg [31:0] cycle = 0;
  reg [0:0] PI_en;
  reg [0:0] PI_rst_n;
  wire [0:0] PI_clk = clock;
  counter UUT (
    .en(PI_en),
    .rst_n(PI_rst_n),
    .clk(PI_clk)
  );
`ifndef VERILATOR
  initial begin
    if ($value$plusargs("vcd=%s", vcdfile)) begin
      $dumpfile(vcdfile);
      $dumpvars(0, testbench);
    end
    #5 clock = 0;
    while (genclock) begin
      #5 clock = 0;
      #5 clock = 1;
    end
  end
`endif
  initial begin
`ifndef VERILATOR
    #1;
`endif
    UUT._witness_.anyinit_procdff_124 = 4'b0000;
    UUT._witness_.anyinit_procdff_129 = 1'b0;
    // UUT.props.$auto$async2sync.\cc:101:execute$131  = 1'b0;
    // UUT.props.$auto$async2sync.\cc:101:execute$231  = 1'b0;
    // UUT.props.$auto$async2sync.\cc:101:execute$237  = 1'b0;
    // UUT.props.$auto$async2sync.\cc:101:execute$243  = 1'b0;
    // UUT.props.$auto$async2sync.\cc:110:execute$135  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$141  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$147  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$153  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$159  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$165  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$171  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$177  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$183  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$189  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$195  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$201  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$207  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$213  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$219  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$225  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$235  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$241  = 1'b1;
    // UUT.props.$auto$async2sync.\cc:110:execute$247  = 1'b1;
    UUT.props._witness_.anyinit_procdff_113 = 1'b0;
    UUT.props._witness_.anyinit_procdff_114 = 1'b0;
    UUT.props._witness_.anyinit_procdff_115 = 4'b0000;
    UUT.props._witness_.anyinit_procdff_116 = 1'b0;
    UUT.props._witness_.anyinit_procdff_117 = 1'b0;
    UUT.props._witness_.anyinit_procdff_118 = 4'b0000;
    UUT.props._witness_.anyinit_procdff_119 = 4'b0000;

    // state 0
    PI_en = 1'b0;
    PI_rst_n = 1'b0;
  end
  always @(posedge clock) begin
    // state 1
    if (cycle == 0) begin
      PI_en <= 1'b0;
      PI_rst_n <= 1'b0;
    end

    genclock <= cycle < 1;
    cycle <= cycle + 1;
  end
endmodule
